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In the case of AD1862 the negative going front of LE (=WCKO of PMD100) triggers the conversion. This signal needs special attention. For the other signals the PMD is really helpful because of it's burst clock operation.

Data is loaded during the WCKO cycle by these signal lines: BCKO, DOL, DOR and all three of them are held at zero when the trailing edge of WCKO occurs. So IMO I don't think they need reclocking, doing that complicates the layout and requires more attention to decoupling...etc....so more problems created than solved.

My oscilloscope is nothing to write home about but anyway here's the link again to that screenshot. The data lines are not present, of course they are active only during the 20 cycle BCKO burst.
PMD100 to AD1862

As for improving the SAA7324 decoder I'll report back when I'm sure it works. I don't know if reclocking there will bring any benefits but you need for sure some level translators (SAA is 3.3V and PMD is 5V logic). I picked up this one: sn74lvc1t45

I want to implement part of this project using a CD650. I2S-wise, can one simply interchange a 7210 for the 7324?
Also, the schema posted in the PMD100 to AD1862 thread is cropped. Any chance you can throw up a fuller version? (I'm especially interested in what got cropped off on the right-hand side.)
Thx!

All right, back to work (holliday is over).
I think I owed some explaining regarding the clocking scheme so I'll start with it. Well...it works as planned!
On the CD-Pro module:
- First I removed the 8.4M crystal and the asociated capacitors, but I kept the 1 meg resistor.
- I tied the SELPLL (pin 24) of the SAA decoder to ground (there's a 10k pull-up that I chosed to remove, it can be let in place though) This disables the PLL loop that is used to generate a whooping 66,xxMhz MCLK inside the chip and lets it to accept a 33.8M signal (crystal or external clock). In our case it is a TentClock transmited through a differential line.

Here is the schematic, simplified to essentials

Other improvements to the CDPro:
- Removed the on board REG1117 and I replaced it with a TPS79433 situated on a small board (area surrounded in green in the previous schematic) On the same board there's the LVDS receiver and the reclocking latch for the SPDIF output.
- Changed some of the more critical decoupling caps for the decoder
- Removed the AKM DAC and the opamp (useless in our case)
- Added some extra heat sinking for the BTL drivers, especially since we use 10V supply for the servo section (for improved readability)

Here is a photo, sorry for the quality.

I also have mounted one analog stage and did some tests with a signal generator (for now). On it you can find the IV stage, the second order filter, the servo and 4 shunt regulators (2 from Guido for the filter and 2 of my very own for the IV) Most of the transistors are dipped in thermoconductive epoxy and fit in heatsinks. DC wise there is no drift and there are no offset issues - right from power-on.

Here is how it looks like:

You da (wo)man! Wow! Thx for the legwork

The IV, here are the final values. I'm running it at 12mA for normal gain (one leg runs at 24mA when the gain is set to +6dB). Resistors with an * are actually combinations R+trimpots that will be replaced in the end with fixed values (after I'll finish the other 3 boards).

Now the filter, a few minor changes with respect to the previous version. It takes for the servo a few good seconds to adjust the output offset especially if it is switched on high gain. But all the measures are in place to avoid the 'big thump'.

And my shunt regulator, I cropped only the positive side to keep it clearer. To get the negative side there are the usual 'sex changes', flip the 'lytics, move the RC filter...etc.

This one was more fun to get right: both sides were oscillating with some op-amps, some other op-amps just wouldn't start correctly, I was getting unreasonable values fot the capacitors with an *....etc.

sidiy:
You may have answered this already but is the topology in the earlier-posted partial schema okay to use (i.e., does it continue to "work" stably thru the evolution of this project)?
P.S. I just want to start off simple for now: Implement part of this project -- say, after decoder and before I/V -- in a CD-650, CD-60, etc. And all on Veroboard, off course!
Thx for the tremendous work/effort thus far!

Yes, as is, the schematic should work fine but there is one issue with the input format of the PMD100.
At the time I copy-pasted the recommended glue logic from the datasheet (page 17 - the decoder is SAA7345 with I2S output)

It seems that I won't need the inverter (U9) and that the LRCI should be taken from the pin 5 - Q output (not /Q).

Here is the result of this test, the traces are:
1: WCLK
2: DATA
3: LRCI
4: SCLK

Anyway I need a couple of days to confirm this (have to reprogram the PIC that controls the PMD100 and to do some soldering)

That is a huge amount of excellent work, sidiy.



Allow me a question, what is the first buffer stage (J1A and J1B) for? Is it really necessary?
I don't see a connection to the output buffer, but I may be missing something.

_________________
Carlos Filipe

"Any intelligent fool can make things bigger, more complex, and more violent. It takes a touch of genius - and a lot of courage - to move in the opposite direction." Albert Einstein

Between the two diagrams, it's a bit hard to tell what clk freq you have going back to SAA7345. Can you clarify?

Hello Carlos,
Good questions, allow me to link an older thread with more info on the subject: What Sallen-Key Filter Articles Don't Tell You, please refer to the schematic that I posted there.

There is an "unexpected" notch in the transfer function of an Sallen&Key filter where the output impedance of the op-amp equals the reactance of the feedback capacitor. Higher output impedance and/or value of the capacitor shifts the notch lower in frequency and the filter may become quite ineffective.

It seems to be our case because the output Z of a J-Fet buffer is quite high, certainly higher than of most op-amps. To mitigate the effect we use the high Idss version of LSK389 (13 to 14mA) with lower values for the source resistors (18 ohm instead of the traditional 22 ohm). According to my measurements in these conditions the notch is at around 605kHz, not really that bad afterall.

Also splitting the tasks between the two buffers might help too (one drives the 'capacitive' part of the load while the other sneaks in and takes a better filtered signal to drive only the actual load) I think that overall it may worth the investment for the extra buffer.

Hello h_m
OK, it seems there is a confusion: the CD-Pro uses the SAA7324 while the example in PMD datasheet uses the SAA7345 only to show how the PMD can be interfaced to accept the I2S format.

The master clock sent to the CDPro is:
- 8.4xMHz for the incomplete schematic, the one you linked
- 33.8xMz in the final built version

The master clock is 16.9xMHz for the diagram in PMD's datasheet

Of course to accomodate these frequencies the SAA decoders must be configured properly.