DIYHiFi.org

See this program to CALC Jitter http://www.xilinx.com/support/documentation/data_sheets/s3a_jitter_calc.zip

Aha, simmconn, the first indication of low jitter - well done! What sort of range is the jitter in?
I'm looking at the US model so SPDIF isn't of concern - take I2S signal off before PCM1793 DAC.
Does it end up good sounding over SPDIF at lower speeds?

I have just bought the USD for $75 delivered and will relock the output with my Big Ben for audition.
Can probably change the output transformer but this won't make jitter any less.

How good are the eye pattern and wave symmetry?

Which would be better, in theory, tapping into the I2S signal from the US model (& feeding it over an inch or two to an internal DAC) or reclocking the SPDIF output signal?

I am not that much interested in theory these days. My own experience dating back to the Assemblage 3 is that I2S is just as susceptible to cable effects as anything else.

I get good results using good relockers.

With the ESS Sabre, PCM, I2S and SPDIF each has its own merits. The integrity and symmetry of waveforms seem to have an effect

And that sounds like what? 1200 ps ?

This is running off USB power so it's not surprising. It's also using a 12MHz crystal of unknown quality. Possible improvements?

I read somewhere that the only Torx units that will do 192KHz are Toshiba & these are out of production!

Ah, Looking in Digikey, I see that there are newer Toshiba units that will do upto 125Mbps

Unfortunately these modules also have a minimum data rate that is too high for (most of) the audio sample rates.

So is there a way out of this dilemma?

way out:
~99% there wont be a 192khz HD format , ever
Its really just a waste of space .
I don know why they put it into HDMI , which is btw, very similar to this china receiver, they claim 200ps but must be worse imho.

Maybe, maybe not - ?
Neil Young Archives vol 1 released on Blue Ray recorded in 24/192
Some others here http://www.2l.musiconline.no/shop/displ ... &cid=&sid=

Jeez, a few posts ago it was 1200 ps jitter now 200 ps

Could be 200 pSec.........




From 1 kHz on up.

Jocko

I have to correct my previous measurement result, because I wasn't comparing apple to apple - the 20dB difference in jitter spectrum levels between the AP and the 01USD was not under the same sampling frequency. The 01USD was running at 192k but the AP was at 48k. So the 01USD's performance under the same sampling rate is better than I thought.

Now the bad news -
I was wondering how they are going to make it with XC3S50A which has only two DCMs inside. First of all the EZUSB-FX2 chip is able to output 48MHz, 30MHz, 24MHz, 12MHz, or a fraction of 24MHz with GPIF - anyway, I think (from what I probed) the 01USD uses only 48MHz and 30MHz from the EZUSB.
In order to generate S/PDIF output at 176.4KHz and 192KHz, the conventional (and low jitter) design method calls for clocks 2x the bit rate, which are 22.5792MHz and 24.576MHz, respectively. The ratio between 22.5792 and 48 is 294/625, and 64/125 for 24.576. Since the DCM has a limited frequency ratio in frequency synthesizer mode (m/n where m between 2 and 32, n between 1 and 32), they'll have to use both DCMs cascaded to generate two different clocks: 294/625 = (14/25)*(21/25), 64/125 = (8/25)*(8/5). Apparently the 176.4KHz and 192KHz families do not share the same DCM ratios. Yet the DCMs ratios are configured at compile time - which means they'll have to dynamically reconfigure the FPGA when playback sample rate changes - Fancy!
Well, that's not how they did it. They used a close frequency for 176.4KHz family, 48*8/17 = 22.588235..., which is 400ppm higher than what is supposed to be. My best guess is that they still use two DCMs cascaded together, one converts 48MHz to 22.5882MHz, while sending a 96MHz 2x clock to the second DCM, which then converts it to 122.88MHz at 32/25 ratio and further divided by 5 externally to get 24.576MHz. That way they have fixed configurations for both DCMs, no dynamic reconfiguration trick.
Evidence? The FPGA is pulling data from the EZUSB chip at a constant rate equivalent to the sample rate, a signal indicating the slave FIFO address is in sync with the S/PDIF output preamble - they didn't have to do this but for whatever reason they did - which spilled the beans. That signal is exactly 1088 48MHz clock cycles at 44.1KHz and 500 cycles at 96KHz. You do the math...

The conclusion? The 44.1k sampling rate family from the 01USD is not exactly 44.1k. Adding to the 100ppm frequency offset from the crystal (my board, yours may vary), you may end up with a 500ppm error. It is still within USB spec. So we have nothing to complain about. You get what you paid for, right?