hifizen wrote:
Call me skeptically hopeful. The DAC may live up to the published performance specs, and probably it sounds very good in a careful implementation, but the marketing claims are clearly lacking 'truth in advertising'. 'Jitter free'? Yeah, and I've got a bridge to sell you....
A little reality check:
Reading through their white paper... the first thing that's obvious is that they're applying ASRC to all incoming data, in order to put it into the clock domain of a local XO. This means that any meaningful comparison should be done against a 'competitor DAC' which is also receiving it's data through an ASRC to bring the data into it's local clean-clock domain.
Still, this by definition cannot be 100% jitter-free, as at some point, the incoming data is arriving at some rate, determined by the source, and thus has to be buffered into the output clock domain, with a tracking mechanism to avoid buffer overflow or underrun... the rolloff frequency for the buffer tracking is naturally a function of buffer size, and by extension, latency through the buffer. So they're up against the exact same wall as all the other ASRCs on the market - AD1896, SRC4192, etc. - at an acceptable latency, jitter rejection can only be achieved above a certain frequency. Below that, the rate conversion ratio must track the relative drift between the the source and output clock domains... In the process, LF jitter from the source becomes hard-coded into the 'non-jittered' output data values. No way around it, the source and output are inextricably linked unless you're willing to accept an audio drop-out while the buffers reset, and loss of lip-sync if the audio goes along with a video stream. My money says the ESS chip's ASRC jitter rejection performance is in the same ballpark as the aforementioned ASRC chips, as that is what can technically be achieved given similar practical design constraints.
The jitter on their DAC side will of course be a function of how good their XO is, and how cleanly the resulting clock is delivered to the internals of the DAC IC. There's certainly no such thing as 'jitter free'. LOL
So there's your bun. Let's talk about the meat, then:
They do claim that their actual rate conversion algorithm is something different from the polyphase filters used in most ASRCs, and that it results in greater accuracy of the output data (-175dB DNR vs -144dB for the AD1896, if memory serves). This, I can believe, as it is certainly known that there are both excellent and very poor ASRC rate-conversion algorithms out there - it is definitely possible to do better than today's real-time chips if the rate conversion is done offline using a PC. No reason a better implementation can't be done for real-time conversion, either, given enough DSP horsepower. So if there's a reason for their ASRC to be better, I think the rate conversion algorithm would be it. I am rather curious what they're doing, if not polyphase filtering. One of these days I'll have to look up their patent.
More bun...
They have an interesting (nothing more than interesting, certainly not better from a performance standpoint, but cheaper and easier, yes) method for SPDIF input decoding, which looks to me like a good way to make a cheap SPDIF receiver, by simply avoiding most of the analog stuff that other SPDIF receivers use (mainly, the PLL). They probably transfer data into the buffer as whole sample words, which avoids the need to capture the timing of every edge. Their implementation also suggests to me that they are strictly dependent on the use of the ASRC (which I presume cannot be bypassed as a result). Not a big deal if it's a good ASRC, but it is one more processing step in the signal chain.
Finally, a slice of cheese and a pickle:
The sigma-delta techniques they're using are also clearly different, and looks promising. It sounds like they're on the right track with regard to how transients are handled. But, I still have to wonder, is any sigma-delta DAC ever going to produce dynamic (transient) output as clean as a good 'ol multibit DAC? Careful dithering applied to a good multibit DAC still seems like the best way to go. Too bad multi-bit silicon is expensive, and dying a slow, painful death.
Hi Chad,
Glad to see the interest in the part. I do have a bit of insight into some of the ways the chip works.
I just wanted to point of a couple things, just for the sake of clarity. Obviously I cant say Exactly how we did the ASRC other than that which is written into the patent. But basically it doesn't use any buffering or FIFO method. THe latency throught the whole chip is 833uS at 44.1kHz sample rate, including the ASRC blob. The ASRC does have to lock onto the input rate, I just did it with a bandwidth of 0.1Hz.
You are right about the SPDIF, when using that input mode, you MUST use the ASRC, when using the DSD or PCM inputs the ASRC is optional and can be bypassed altogether.
The DAC used a 6/7/8 ot 9 bit noise shaped modulation before going into a DEM scheme. So I guess it is a multibit DAC in that regard.
I am happy to answer any questions that I am "allowed" to, basically, what that means is I cant go into too much detail more than what the patents diclose. Anyways, hope you get a chance to critique the DAC.
Thanks
Dustin
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Would you say the performance is then limited by the XO and output stage?
