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PostPosted: Thu Aug 07, 2008 4:05 pm 
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Gang,

When I designed my first mother board for a PC it was like 1990 I think. They let me do whatever I wanted just to make sure the magazines would like the output. It was pretty good for that time period.

The next four though were a pain in the a(*)(_)__+))_ .... I had a cost accountant strapped to my desk. "if you add that it will raise the cost of good sold by xxx$." but it will work so much better....

It really took any fun out of it... But most of the engineers who helped out really didn't understand why I was doing stuff. I think the main reason was they were off doing there own thing in their heards (well like me audio...). I had 165 engineers working for me at one time. Mostly software and I will tell you they are not good at telling a lie and ctl-alt-del was a common occurance when I stepped into peoples offices.

Ahhh it doesn't matter in audio it's only money.

Thanks
Gordon

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PostPosted: Thu Aug 07, 2008 4:33 pm 
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gmarsh wrote:
...The 20MHz oscillator had a 56 ohm resistor on its output and was almost dead-center in the board. The output of the resistor was split 2-3 different ways and made its way around the board.

But at one of the targets, which was a fast CPLD chip, was acting like it had a 40MHz clock. We scratched our heads for a while. Then I got a fast scope and had a peek. It turns out it was a "round-trip reflection" on the 20MHz signal - an edge would go out one clock trace, reflect off the end, come back past the oscillator and onward to the CPLD. There the reflection would "dip" the clock enough to double-clock the CPLD. I yanked the 56 ohm resistor, cut the trace, air-wired two 33 ohm resistors on from the oscillator. Board started working correctly.



This is a scary example why every clock line needs a series resistor, right at the output of the oscillator (or buffer).
Excellent stuff, gmarsh!

Just stay clear of Gordon's cost accountant. :finga:

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PostPosted: Thu Aug 07, 2008 5:14 pm 
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gmarsh wrote:
I think you're describing a production/efficiency manager.

Maybe I am but that's not their title or professed function.

To me, the problem is two-fold.

One is that most engineering students learn by doing simulations, made with ideal models and circuits. The reasons why it's done this way and why this approach isn't the whole story are probably all too familiar.

The second is that there is just an overwhelming incentive to be more of a business person than a techie. I will almost guaranty that engineers and managers (and probably women at parties and in bars) will say that an MBA is more important than an MSEE or whatever.

You're right - this is too far off the topic; I'm done.


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PostPosted: Thu Aug 07, 2008 5:21 pm 
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Well, it depends on how critical the outputs are. I would not mix the clock to the DAC in with all the rest of the stuff. That clock is too critical for any corruption.

No, let's leave this discussion here. It melds into some of the other stuff I am working on. Specifically, the PCB for the PMD100 and AD 1862.

They will be on 2 separate PCBs. Not sure that everyone who wants a '1862 is going to have a HDCD chip in their junque boit. So, how to handle the task of taking signals from A to B is the issue. (Besides, the layout starts to get messy with all 3 on one PCB. Hard to make equal length lines, and that was one of my original lofty goals.)

After thinking about this a long time, I am considering putting only one DAC on a PCB. Not to make more $ (which will be low-profit, I can assure you), but rather to extract everything that I can in terms of performance.

If I make 2 PCBs (actually 3, to be perfectly correct), my plan is to run a ribbon cable for the digital lines. But, there is no way to control the lengths. So, I have to consider how to drive unequal lengths of cable, wrt to reflections.

So, let's say that I drive the clock from the HDCD with a picogate for each DAC. It is now inverted. OK, I can reclock at the DAC, and take care of the inversion there. Ah, but I wasn't planning on reclcocking the data. Since the '1862 has a serial-to-parallel converter inside, the WCK is effectively do the reclocking when it latch-enables the data.

So, I am curious as to how you guys think. Granted, while I don't expect Gerhad, Gmarsh and CG to be interested in buying PCBs, we should welcome their input. As will be yours.

So, I am interested in your thoughts. Now is the time to speak up. In any case, this should give us all something to mull over, and hopefully expand our knowledge and understanding.

Jocko


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PostPosted: Thu Aug 07, 2008 5:25 pm 
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CG wrote:
The second is that there is just an overwhelming incentive to be more of a business person than a techie. I will almost guaranty that engineers and managers (and probably women at parties and in bars) will say that an MBA is more important than an MSEE or whatever.


Forget that part: still being employed when you are over 45 is a real challenge. If being a nerd wasn't enough to scare the babes off, being unemployable when you have grey hair will really run them off.

OK, enough social commentary. CG, you are banned to The Pub for the rest of the afternoon! [joke]

Jocko


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PostPosted: Thu Aug 07, 2008 6:24 pm 
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Jocko Homo wrote:
Granted, while I don't expect Gerhad, Gmarsh and CG to be interested in buying PCBs, we should welcome their input.

I am banished for the moment, so this post will have to be post-dated...

First, I'll keep on sounding like that old 78 with a huge scratch in it and suggest that a track-and-hold circuit in the analog section would alleviate every bit of this.

How about adding a high frequency termination at the DAC (receive) end as well? Won't that minimize the reflection? I suppose that you could even AC couple each line with a cap and use a 2:1 bias network on the DAC input to set the switching point properly. I don't know how well that works with the AD1862, but I know it works real well with some modern DACs used at higher clock frequencies. Like about 200 MHz. Sine waves work so much better for clocks, as long as the duty cycle is 50%.

What was the part number for that Analog Devices amplifier that had the dual floating inputs that were current summed? :scratch:

I may well buy these boards. Especially if I can figure out how to do async transmission via USB...


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PostPosted: Thu Aug 07, 2008 6:54 pm 
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CG wrote:
To me, the problem is two-fold.

One is that most engineering students learn by doing simulations, made with ideal models and circuits. The reasons why it's done this way and why this approach isn't the whole story are probably all too familiar.

The second is that there is just an overwhelming incentive to be more of a business person than a techie. I will almost guaranty that engineers and managers (and probably women at parties and in bars) will say that an MBA is more important than an MSEE or whatever.

I don't consider the first problem to be a problem.

Good engineers are "double-educated". The first education you'll get is in university - you'll get clobbered with ideal models, SPICE simulations, antenna theory, transmission lines and all sorts of things. Even though this is all "theoretical", these theoretical models are 99% accurate in describing how the world works and this knowledge is a powerful tool.

The second education is when you're out of the theoretical world and in the real one. You build your first prototype and it doesn't work correctly, so you talk to a few people who are "in the know". It's during this time that you learn that R's aren't R's, C's aren't C's, but almost every passive component you work with is actually a RLC circuit with different values for each.

And you learn the unfortunate truth that all traces are transmission lines. Angry ones that will do everything they can to get back at you. They'll spit signals back at you, radiate them, introduce return currents in places you never imagined, you name it. But you'll test, measure, understand and you'll find yourself coming full circle to the theory you learned in school.

...

I won't get into the second "problem", because there's about half a dozen different types of engineers.

Jocko: I'll think about the AD1862 thing a bit.


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PostPosted: Fri Aug 08, 2008 2:02 am 
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Jocko, the single pcb approach looks interesting I guess we might be interested in four single pcb's. Actually on any other solution you may wish to make available... :grin: We don't intend to reclock the Data or BCLK lines either, anyway, when using a PMD, WCLK arrives when these are silent. However we intend to reclock the WCLK with two 'picogates', each one being close to the corresponding DAC. Now the question arises: one aspect that will require special attention is how to transmit the reclocking signal (33.8M in our case) to each of the flip-flops via ribbon cables...scary stuff (for me, I mean :wtf: ).

My plan is (or was - not sure yet) to place the MCLK osc. between the DACs on the same pcb and to derive a (buffered) line towards a divide by 2 (filter) and then 4 (CDPro) and then another line (buffered?) split towards the DACs/flip-flops....
A possible advantage is that MCLK will cross the other lines at 90deg and that diferent lenghts for the WCLK coming from the filter should not matter since they're reclocked/cleaned by a good clock. If my approach is wrong...well, plans can change.

For those of who haven't followed the forum...we're still 'Building ourselves some CD-Players' ;)


Last edited by sidiy on Fri Aug 08, 2008 2:26 am, edited 1 time in total.

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PostPosted: Fri Aug 08, 2008 2:17 am 
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One PCB may sound better, but I have enough problems with just 1 DAC per.

OK, if I didn't care about trace lengths, and all that.............traces going all over the place, etc. But, I think more folks could use a '1862 PCB than HDCD, so it makes more sense for me to do it that way.

But now that I think about it.............I need to add an extra resistor to the clock PCB for 2 clock lines to the DAC(s). I can make a ribbon cable with equal lenghts for both '1862 PCBs. I may stack them in my design.

OK, along those lines.............make +/- 12 V and +/- 5 V supplies on 1 PCB to supply power for the '1862? Or load up each PCB with a bunch of regulator stuff? (I may use some SMT stuff here, as the resistors won't have much voltage across them. We may be able to tolerate a few nV more of noise.)

Jocko


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PostPosted: Fri Aug 08, 2008 9:17 am 
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Jocko, do I understand you right that you intend to make one PCB for each AD1862 dac chip?
Something may be escaping me but I fail to see any advantage in doing that.
Clock transmission, grounds...
Houston, one PCB for both dacs please.
Regulators onboard.

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PostPosted: Fri Aug 08, 2008 4:43 pm 
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Four regulators and equal lengths for critical off-board connections............yeah, it is escaping you.

It may need a gazillion jumpers if it all goes on one. Mainly for all the supply traces.

Jocko


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PostPosted: Fri Aug 08, 2008 6:11 pm 
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I see...

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PostPosted: Sat Aug 09, 2008 6:39 pm 
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sidiy wrote:
However we intend to reclock the WCLK with two 'picogates', each one being close to the corresponding DAC. Now the question arises: one aspect that will require special attention is how to transmit the reclocking signal (33.8M in our case) to each of the flip-flops via ribbon cables...

Wouldn´t it be best to place the clock and the reclocking flip flops on one board, then go with ribbon cables to the separate AD1862 boards?

In other words, much easier to maintain signal integrity of the wordclock, at 8*FS, than the scary 768*FS...


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PostPosted: Sat Aug 09, 2008 6:56 pm 
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Jocko,

In my opinion, separate boards is good. More flexibility. This is DIY!

If I understood correctly, the wordclock will come from the PMD100. I ask you: can it be reclocked?

So, what do you think about the clock+reclocker idea. Both on one board. One problem I see is that some guys need 256*FS, some need 768*FS / 384*FS, to go to the cd player.

Is it possible, maybe, to accomodate everyone with 768*FS? Division by 3 is possible, isn´t it?


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PostPosted: Sat Aug 09, 2008 9:22 pm 
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I could make a reclocker PCB, as a stand-alone for everyone else. Maybe.

This is strictly a 256 x Fs, and AD1862 affair. I only need to reclock the LE (WCK) for it.

Been working on it all day, trying to get equal traces for critical stuff that has to split. There are going to be a ton of jumpers.............all for power from the various regulators. Those aren't critical.

Jocko


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