DIYHiFi.org

This is what happens when you disturb the space time continuum. At least without a license.

Be thankful your analyzer isn't one of the real new ones. The ones with a Windows based computer built in.

I was trying my hardest not to bring up that disturbing fact.

Jocko

OK, time to be stupid again, or still.

This thread has been great, learned a bunch and it's interesting.

So, how low of a noise can we hear via the clock? Jocko you've posted earlier that with Guidos set up; i.e. clock and reg, that his unit will get to a few pS of jitter. Assuming that a Tent clock is run from your reg that number should go way down. Will it matter much assuming that the rest of the system is going to add jitter of it's own? I'm also assuming that since you and Gordon keep pursuing this that jitter in the 1-2 pS range or less can be heard, or you guys wouldn't be busting your butts.

Now the next question Jocko; What happens if your reg is used to power a AD1862 and another one for a PMD100? As an example. Is the jitter from them also going to be reduced that much? I've assumed that running each chip on it's own reg is to keep the switch noise from going from one chip to another...

I understand what the low 1/f from the reg is doing, but, at that low of a frequency is it correlated or non-correlated jitter that's produced? I'm assuming the answer to that is dependent on correlated or non-correlated noise.

Mike

I think that Guido has probably put enough work into his stuff that his noise level is comparable to what we are trying. So, I would not expect much, if any, of an improvement.

As for powering mixed signal chips............

I think that many of them will have so much stuff going on, in many cases with only one supply and ground lead, that there will be substantial noise on the supply rail.

Maybe for the '1862 digital supply pins. I have not gone to the effort of testing that yet. The current draw is very low, so it might be of some benefit. Especially when it comes to the serial-to-parallel converter as the latch loads the data. That is something that I will look into. Maybe.

The analogue pins are +/- 12 V, so I have other things in mind for that.

Jocko

Or any other digital filter, for that part.

I don't know how many, if any, guys have read Howard Johnson's books. I have read parts of both of them. Now, while he is talking about high-speed "black magic", how different is that from high-performance audio?

Let's think about the 2 output pins that are common to both channels. The odds of having the exact same length wire or trace for both channels is really low. This will cause some minute reflections, but at different points in the waveform. It is stuff like that which is responsible for funky looking waveforms.

So, what can be done about it? Well, one option is to put a picogate, with equal trace lengths, to 2 separate gates. At that point, there will be very little interaction with 2 traces of very different lengths.

So, some of you may remember some low jitter clock distribution schemes that I posted over at The Pub. But what about driving a whole bunch of different length wires?

Easy: 2 picogates. One goes to the DAC, directly. The other goes the other gate. It has a resistor tree on its output. Those outputs go to non-critical places in the chain. They should be able to tolerate some crud on their waveform, as long as you have a stable and clean clock directly at the DAC.

Make sense? Maybe it is not all that practical. But this is DIY. And part of the goal is to make it better than off-the-shelf over-hyped high-end crapola.

(Their exotic approach is usually to use all 6 gates in a hex inverter. One supply pin, one ground pin. Not bueno.)

Jocko

Trying to explain this to most "real" engineers is pretty futile. They essentially demand the equivalent of double blind testing to prove that it matters. Then the arguing ensues. Of course, they never actually try it to see for themselves. I'm not talking about audio applications, either.

On a broken record topic: Has anybody tried using a track-and-hold circuit at the output of the I-V (or part of it)? A clean clock to that should minimize the collected jitter from the mixed signal parts.

Got it.

Dude, what???

I have a 1uF on the output of mine and don't see anything like that. I thought you meant the RC cap.

~~~~~~~

Mike,

Here's my take on this stuff. To evaluate most of the dac chips I tried I used some of the eval boards they made. Most of these have standard 3 terminal regulators and are not strick of their usage. They are also usually pretty far from the device too give you clearance to muck with the chip.

Next I would build a board with my altered maxim regulator type and then check it out. For the analog supplies I did simple non feedback led rc emitter follower stuff. Those usually down in the 200nv at 5hz. I would use standard ceramic crap parts and put them together.

After getting them too work I would send them out to beta sites.

Next I would sit around for hours changing caps and stuff and changing the board. Then get pre-production boards made.

With these I would then test the eval board the proto board and the pre-production boards on both the Prism dScope III for jitter, response, thd and stuff and the HP for supply noise.

The Jitter would fall pretty much on each one of the iterations. Thd and response were pretty much the same for eval and proto but would come down for the pre-production about 10%.

The response from the beta testers is what is interesting. Most really liked the proto boards. But when they received the preproduction units I was getting emails like 4 a day.

I think this stuff pays back big time...

~~~~~~

Jocko I will give you a call about my HP later today. Seems the problem is that when I short the inputs the noise is higher than the measured noise which of course when subtracted freaks the unit out. I tried it on PSD and Spectral and it always does the same thing.

I have to get some product out.

Thanks
Gordon

_________________
Gordon
Chief Scientist
Wavelength Audio

What I did was to take the circuit shown in the app note, and load it into a simulator. I treated the regulator like an opamp. Since I didn't know what the actual operating parameters were for the regulator, I left the open loop gain and unity gain bandwidth as variables and tweaked them until I got what Jocko had shown on his plot.

Then, I adjusted the RC capacitor and the output cap to get rid of the peak. That's where the 0.1 uF at the output came from; I thought that to be more representative of what would really be used. Then I changed the 100 uF until the peak was gone. That was at about 220 uF.

Now, I am just confused.

I do think that the regulator needs to be loaded by a couple mA so that the operating parameters stabilize. Maxim doesn't state a real minimum output current, but they do only spec the load regulation performance from 1 to 500 mA.

There's three types of jitter involved here. One is random jitter, caused by white noise. Then there is supply related jitter - like multiples of the 60 Hz supply - that adds mixing products to the DAC output. Then there's digital switching related jitter that also causes additional unpleasant mixing products. Some of these are likely program related in an abstract way. You probably can envision the effects of each on the musical reproduction. Ironically, it's pretty much the same thing as with amplification stages, only worse. (This is why a T-H system might be better...)

Keep it coming guys. This is great stuff.

I've ranted before about regulators. Glad to see there is still more to it.

CG,

I use the LM317L and load the output to draw at least 5ma. When I let it fly like maxim did the noise went up about 20dB.

So far I get about 22nv at 5hz raised to about 700nv at 0.125mHz and on the other end it goes down to like 12nV at 50hz and stays that way all the way out. I have only a 1uF on the output then ferrite to OSC22.5792 and another 1uF and the same to the OSC24.576. One or the other are on but not both and these things draw between 4.8ma and 5.3ma.

Input is 8V and output is 3.2v. I found the oscillators like this voltage better than 3.3 or more. Got me...

Another thing to think about in regards to jitter maybe digital filters. I was telling Jocko yesterday that with the Benchmark since it uses an upsampler @ 110khz that the jitter spectrum was more irratic than matched sidebands. I think that is because of clock interaction between the input sample and the output sample going to the dac.

We have to realize that jitter can be had at the input to these devices that cannot be fixed by digital filters or upsamplers.

So if you use a synchronous clock to the filter it may work much better than an async one. With async then you are going to get different system jitter results at different Fs rates.

Thanks
Gordon

_________________
Gordon
Chief Scientist
Wavelength Audio

I have measured the leakage of various caps: FCs, FMs, a few different types of Black Gates, along with the solid polymer types. I can concur that 1 order of magnitude worse leakage is a reasonable assumption.

(Measure it yourself if you don't believe us.)

Jocko

I missed that trick last time I perused the article. A good idea, indeed. Especially when you consider the above post.

Jocko

Gang,

Spent hours this morning with the HP turned it off and worked on the Prism. Here is what I get...

Supply 1: 5V, 3 pan green led's 4k99/100uF RC, 2n5089 all smd between 120nV at 10hz down to like 70-80nv above 100.

Supply 2: 3.2v modified maxim, 1uF output cap 120ohm ferrite 1uf bypass into 24.576 oscillator active: 26.12nv at 10hz down to like 18nv with a couple of small (less than 10nv humps or dips at 48k and 96k, expected active.

I don't see any humps like Jocko got on his.

HP still giving me fits... shorted input more than measured input. Makes Spectral-TRACE1= ??? (actually displays that).

Going to turn off the instruments now and try and get something done.

Thanks
Gordon

_________________
Gordon
Chief Scientist
Wavelength Audio

I think you're describing a production/efficiency manager. "Why are there so many parts on this board? If we remove this and that, will it affect the product performance? Do we really need so much decoupling?"... yadayada. Thankfully we don't have one of those folks where I work.

Jocko's totally right about clock distribution, and using picogates for proper fanout. Rather than explaining why I agree, I'll just give a narrative.

At university, I worked on a board was designed by an EE doing his masters. The board had a 20MHz metal can oscillator, and this signal was used in a few different places around the board. It was also a physically large board, probably 12x16'. The 20MHz oscillator had a 56 ohm resistor on its output and was almost dead-center in the board. The output of the resistor was split 2-3 different ways and made its way around the board.

But at one of the targets, which was a fast CPLD chip, was acting like it had a 40MHz clock. We scratched our heads for a while. Then I got a fast scope and had a peek. It turns out it was a "round-trip reflection" on the 20MHz signal - an edge would go out one clock trace, reflect off the end, come back past the oscillator and onward to the CPLD. There the reflection would "dip" the clock enough to double-clock the CPLD. I yanked the 56 ohm resistor, cut the trace, air-wired two 33 ohm resistors on from the oscillator. Board started working correctly.

I'll leave the lesson to the reader.

Anyway, this is off-topic... maybe this discussion should be moved into its own thread?