DIYHiFi.org

Was just wondering if anyone's seen this:
http://www.maxim-ic.com/quick_view2.cfm/qv_pk/4421/t/al

Yeah yeah, another MPEG-2 based audio clock generator... but this one has a VCXO input. This strikes me as rather useful for reclocking use.

Any comments?

Its usability for this purpose would be best described by its corner frequency which is not shown, and we probably shouldn't blame manufacturer for this because this part is rather intended for use as a clock generator and not as a jitter attenuator.

Other than that, its intrinsic jitter obviously decreases as an output frequency increases and is also related to the "scaling factor", so a lot of it will depend on the actual implementation. A 100pS at 11.2896MHz, and this is the RMS value, is neither great nor really bad, however you have to remember that this is a PLL so you should expect this is mostly 1/f jitter.

Has around 100 pSec at 11 MHz out. Nope.......way too much.

Yeah, I know, it shows that if you go to a higher frequency that the jitter goes down.......

It does, but the phase noise will not go down. The higher the frequency, the lower the jitter must be the same as the jitter at a lower frequency.

Answer your question?

(Translation: I don't like it any more than any of the other PLL clock gen schemes. Maybe if you make DVD players by the millions.........)

Jocko

It does indeed. The main part that caught my attention was the ability to be "pulled" like a VCXO oscillator which would allow for phase alignment with the original SPDIF signal.

I've been looking at reclocking circuits as shown here, and whats always stumped me is alignment of the two clocks. Then I looked at Jim's HagDac circuit which takes care of this nicely using a VCXO. The problem here is I can't seem to get any VCXO's with frequencies suitable for 44.1/88.2KHz, only ones suitable for 48/96KHz (12.288MHz). So, I was exploring alternatives.

The other thing was that I don't really want to be locked into Redbook only frequencies - primarily my DAC will be used with my PC, so I'd like to be able to support whatever it spits out without having to resample at odd rates.

Tent stocks VCXOs suitable for audio frequencies.

In the current project I'm working on with other guys from here, we will have two clocks, one for 44.1k and one for 48k frequencies, and the CPU will decide which one to use, probably by only powering one at a time to avoid interferences. Both could be plain XO's or VCXO's, this is not decided yet. I believe the DAC should be able to use a SPDIF-only input, for convenience, but either we will do it right (VCXO) or label this as a convenience-only feature and slap an ASRC. We'll have enough options for slaving the source already, and I'd rather deal with XOs rather than VCXOs which have an extra path to inject jitter...

As for the chip this topic is about, I agree with Jocko.....

> I've been looking at reclocking circuits as shown here, and whats always stumped me is alignment of the two clocks.

Actually, if you use the simplest way of making a slaved source, which is to send a clock to a CD player or a SPDIF-encoded clock to a soundcard, you then use your SPDIF receiver in slave mode, which means there is no clock pkase issue. CS8416 contains a double-buffer (a 2-sample deep FIFO if you will) which takes care of that. So, no clock phase problem (I checked that in my previous DAC and can confirm that it works as advertised).

Have looked at that, but spending £60 on two VCXO's is way out of my budget im afraid No offence to Guido, i'm sure his parts are top notch but I can't justify the price sadly. The £/EUR rate sucks in cases like this!


This is exactly how I'd do it in this case. Getting a 48KHz based oscillator - no problem, Farnell and RS stock those... but getting a 44.1KHz based one, forget it.


OK, well the samples cost me nothing



I don't think I can really do this. One of the sources will be an iMac and opening it up to inject an audio clock into that is out of the question, although it does have an SPDIF input, MacOS X doesn't have any way of slaving clock! Another point is that I may put a USB input on the DAC using PCM2706, and use it's i2s output - i'm aware this is also affected by jitter due to how the SpAct clock recovery from USB works, and I would want to reclock it too.

Ah, well, if your iMac has a SPDIF input, you should check, perhaps it slaves automatically to whatever you send it.

To test this is very simple :

- Get anything that has a SPDIF output (but not your MAC), let's say it's a CD player
- Plug it in the SPDIF input of your Mac
- Connect scope channel A to the Mac's SPDIF INPUT and scope channel B to the OUTPUT
- Trigger on channel B
- Unplug CD player from mains
- Play music on the iMac (you see SPDIF on the scope)
- Power up CDP, insert CD, play

If the two SPDIF traces are locked, the iMac is synced to the input SPDIF, you are lucky. If they are not, it does not sync, you are unlucky.

I can't - the in and out are toslink

But i've a feeling they don't lock anyway. The chipset used is the Realtek ALC885, hardly high end although I must confess I was impressed with the quality of the line out, considering. They MIGHT lock using the Windows drivers, but that's no good when I want to use OS X. Apparently, they also have really shitty latency problems.

I guess I am not shooting for absolute lowest jitter technically possible - just better than the crap that comes out of a sound card normally, and thus better than simply using DIR's clock as it is. I'm also not set on using CS8416 - using DIR9001 (but this means external muxing) or the WM8805 (if I can get one) is possible, I'm figuring that a clock-referenced reciever is better, but again I could be well off.

Toslink IS spdif on optical. A pair of $3 TORX/TOTX optical transceivers is all you need. You can do the above experiment with an optical-out CD plaler then

Most probably it is able to synchronize to an external clock. How else would you use your computer to perform effects on incoming digital audio ?

Yeah I know toslink is spdif but it still makes it a pain in the ass

Honestly, I don't think Realtek thought about that application. I'm surprised it even has SPDIF in at all. I have read on several music forums (people using Ableton and such music packages) that the Realtek chipset absolutely sucks for latency. My guess is they don't clock lock and they simply require you to have a large buffer to process audio - hence the poor latency.

Anyway, I'll stick with the idea of cleaning up the recieved clock. I'd really like to get my hands on that WM8805 but nowhere has any of them, not even Wolfson's direct sales!

There :
http://www.profusionplc.com/pro/gex/pca ... WM8805GEDS

Damn, I thought I'd checked there too Thanks!

Jocko pointed it out already, but I'll repeat. The MAX9485 contains a silicon-VCO PLL, and the phase noise performance of the chip, as expected from anything with a silicon VCO, is crap.

The parts to do a proper "jitter cleaning" of a SPDIF derived clock have been available for a while. Here's my recipe.

(1) VCXO. Make sure that it's an actual quartz crystal inside at the frequency you want; programmable VCXO's, and even some specified-frequency VCXO's tend to have things like 19.44MHz commodity crystals inside and a silicon PLL synthesizer to generate a phase-noisy 24.576MHz from that. Go through datasheets and find one advertising <=1ps of phase noise, that's the one you want. Also try to get one that's pullable at least 100ppm.

(2) PLL chip. I'd use an Analog ADF4116.

(3) 3rd order passive loop filter. Google for "Dean's Book", it's an application note written by a National Semi PLL engineer which is a very good resource for doing PLL design. You'll want to aim for a PLL corner frequency around ~10Hz.

Get a (free) copy of ADISimPLL from the ADI website to test the loop filter you come up with.

(4) A microcontroller to configure the PLL chip. I usually use a PIC12C508A for tasks like this.

This will give you a clock, but you may run into metastability hell if you try retiming a jittery I2S clock with it. Doing proper synchronous resampling requires a bit of extra logic to make sure that your logic levels are flat during sampling.

Maybe I'll post a full circuit diagram of a synchronous reclocker sometime, given enough interest.

To be quite honest, designing a PLL is over my head. I'm also quite limited on what VCXO's I can get, as I said earlier in the post, getting ones for 48KHz and the like is easy, getting ones for 44.1KHz is impossible. I also don't want to be locked into one source rate.

I'll probably back off and stick with an ASRC, which would be better than nothing!

It's tough to beat an ASRC (with a suitable clock on the output side) for jitter rejection. Only thing is, you're running a digital filter on the signal going through it which some purists may find objectionable, and an ASRC won't pass HDCD. But if that doesn't bother you, go for it.

You could build your own VCXO using a 74HCU04 or equivalent, 22.5792MHz crystal, varactor diode and a couple of passives. Only thing is, you'll need to borrow a frequency counter to proof your design's pullability and determine the gain slope.

I have a few companies I deal with professionally that make custom VCXO's, but I'll probably have to order 10 or 25. Hmm... maybe I'll design a reclocker board, "group buy" the VCXO and sell it at the other place.