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 Post subject: Re: loops!
PostPosted: Wed Nov 15, 2006 10:29 am 
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MrJam wrote:
Hi Carlos

You should go back to a integral ground plane!


OK. Bad idea, this splitting...

MrJam wrote:
..or to a double layer with top layer full copper (a big step forward)!


Certainly.
I thought about it, but didn't decide yet if I follow the path of ease of fabrication (single-layer) or make a better board (dual-layer).
Nevermind, I'll make a dual layer board.


MrJam wrote:
Place a gnd pin between signal pins in the connector to ensure a proper return path.


Ok.

Btw the board is ~11x4cm, not 10x4cm, as I said before. Didn't see well. Too much bad music lately, from the other thread.

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 Post subject: Dual layer
PostPosted: Wed Nov 15, 2006 11:41 am 
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All currents return to the top groundplane.
The bottom groundplane is just for shielding.


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 Post subject:
PostPosted: Wed Nov 15, 2006 11:43 am 
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Hiding the top groundplane, the board looks like this:


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 Post subject:
PostPosted: Wed Nov 15, 2006 2:33 pm 
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Hi Carlos!

The shielding isn't really effective this way. You should place some vias (lot is better but difficult for diy!) across the top plane and the copper fills in the bottom. The fills have to be at the same potential at HF, range were little track inductances become large impedances, creating antennas.

I'd use the bottom layer only for tracks.
Maybe the section were some shielding - a sort of guard trace - is useful is the regulator one, to avoid RF picking of sense/adj pins. :roll:

I understand your point about through-hole ..but why don't you use smd caps at least for bypassing? ..and only one electrolytic close the supply, without the 100n film/cer (they resonate together and maybe in your scheme) It's worth it!


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 Post subject:
PostPosted: Wed Nov 15, 2006 2:50 pm 
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Carlos,

You might gander over to the BYPASS thread. Over there it was pretty well debated that putting small cermics in parallel with say low ESR caps was a waste of time. The new Polymer Alu ulta low ESR caps seem to test the best for this kinda stuff.

I am finishing up my latest dac that has modules on it for upgrading. What I did there was use a DIN 44 where almost all of one side was ground the other side signals. Just like high speed computers this works much better putting some clocks next too each other.

One note about solid grounding on the ground plane. If you have the capability of doing thermal traces (X connected) to the plane it makes it much easier to solder. In some cases you want a solid but on most you can get away with thermal and avoid cold solder joints.

Thanks
Gordon

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 Post subject:
PostPosted: Wed Nov 15, 2006 5:17 pm 
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MrJam wrote:
I'd use the bottom layer only for tracks.
Maybe the section were some shielding - a sort of guard trace - is useful is the regulator one, to avoid RF picking of sense/adj pins. :roll:


So, no bottom groundplane?
I would prefer this, instead of filling the board with vias.

MrJam wrote:
..and only one electrolytic close the supply, without the 100n film/cer (they resonate together and maybe in your scheme) It's worth it!


Ok.
I removed the ceramics and made the board a few mm smaller. :shock:

Gordon, I remember that thread. But even then I thought the ceramics would be useful on this circuit.

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 Post subject:
PostPosted: Wed Nov 15, 2006 5:38 pm 
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Changes...


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 Post subject:
PostPosted: Wed Nov 15, 2006 5:44 pm 
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Without the top groundplane.


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 Post subject:
PostPosted: Wed Nov 15, 2006 6:54 pm 
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Apparently your PCB software supports thermals around pads (they're there on the passive parts) but they seem to be missing on the IC pins...

It is difficult to solder stuff while the plane acts as a very large heat sink.

Apart from that, it looks good.


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 Post subject:
PostPosted: Wed Nov 15, 2006 8:17 pm 
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Yes, I was in a hurry and didn't finish it.
I posted just for you guys to have a look at it.
The software is ExpressPCB. I find this software the most quick and intuitive to use, but it's limited. It free, can't ask much.
I have others, but no much patience and time.

BTW I just figured that the spacement of the connector pins is not right.
I'll have to make a custom connector on the software. Stupid software... this connector is pretty standard stuff.
I will update soon.

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"Any intelligent fool can make things bigger, more complex, and more violent. It takes a touch of genius - and a lot of courage - to move in the opposite direction." Albert Einstein


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 Post subject: Smaller!
PostPosted: Thu Nov 16, 2006 1:51 am 
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PS: still gotta check that connector.


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 Post subject:
PostPosted: Thu Nov 16, 2006 8:40 am 
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Hi Carlos

I suppose Gordon is talking about caps like SP-Caps from Panasonic - L series seems very good!
Don't use big can electrolitics to bypass digital ICs, too much inductance.
SP Caps (L) datasheet states 600pH series inductance.
Otherwise use smd MLCCs.

What about this layout?
I added:
- HF shunts to the chassis;
- MLCCs for bypass;
- a break in the plane between the supply area and the digital area;
- electrolitic cap at the regulator out, not too low esr here to avoid oscillations.


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 Post subject:
PostPosted: Thu Nov 16, 2006 11:37 am 
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MrJam wrote:
Hi Carlos

I suppose Gordon is talking about caps like SP-Caps from Panasonic - L series seems very good!
Don't use big can electrolitics to bypass digital ICs, too much inductance.
SP Caps (L) datasheet states 600pH series inductance.
Otherwise use smd MLCCs.


Hi MrJam,

The ferrite beads I'll use have 80 ohms impedance at 100Mhz.
I don't know their impedance at lower frequencies, but the use of electrolythics is because I think some capacitance is needed.
These chips have fairly bad PSRR.
100uF is overkill, though. I agree.
Look again, there are lots of options now!

MrJam wrote:
What about this layout?
I added:
- HF shunts to the chassis;
- MLCCs for bypass;
- a break in the plane between the supply area and the digital area;
- electrolitic cap at the regulator out, not too low esr here to avoid oscillations.


Ok, done.
Is there really a need for two HF shunts around each hole?
I really need some clearance there.
What would be a good value to use, 47nF?
Thanks for looking at this.

PS: the connector is perfect. What wasn't perfect was the printer driver. :roll:


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 Post subject:
PostPosted: Thu Nov 16, 2006 2:03 pm 
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Hi Carlos

You misunderstood what L means! It's the suffice of the latest/low esl series of Panasonic SP-Caps (solid polimer aluminum). Download the datasheet. They seems good speced. I'm completing a new order from Digikey with some to experiment. I'll post some measurements in the future.

The chassis shunt is better with a star of four caps (something like 10-100 nF) around the mounting screws - made of metal of course, and connected to a metal stand. Don't add tracks to this connection, they means series inductance.

Don't you think 100uF after the regulator store enough charge?
Electrolitycs // mlcc(multi-layer-ceramic-capacitor)/film is a resonant tank. You're warned!

The layout I suggested changed the jumper in the top layer that produce a bad slot above the signal tracks (let always think about the return currents) with a wire jumper. Did you notice it? What's your opinion?


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 Post subject:
PostPosted: Thu Nov 16, 2006 2:47 pm 
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MrJam wrote:
Hi Carlos

You misunderstood what L means! It's the suffice of the latest/low esl series of Panasonic SP-Caps (solid polimer aluminum). Download the datasheet. They seems good speced. I'm completing a new order from Digikey with some to experiment. I'll post some measurements in the future.
...
Don't you think 100uF after the regulator store enough charge?
Electrolitycs // mlcc(multi-layer-ceramic-capacitor)/film is a resonant tank. You're warned!


Yes, I understood very well that by L you meant the low ESL of those caps.
I mentioned the ferrite beads anyway, because they are after the reg and I'm not so sure if a small 100nF cap after it will store enough charge. These chips have low PSRR, but I suppose that the current they draw from the PSU is fairly constant.
Anyway, when I said that there's several options now I meant that only one is to be used.
The options are: 10uF through-hole or SMD electrolythic (did you notice the solder pads behind them)? OR a mall MLCC under the chip. These are not meant to be used in parallel.


MrJam wrote:
The layout I suggested changed the jumper in the top layer that produce a bad slot above the signal tracks (let always think about the return currents) with a wire jumper. Did you notice it? What's your opinion?


Ah, I didn't notice that.
Yes, it makes all the sense, you don't break the ground plane and that way you avoid the currents to go in turns to reach the ground pins on the connector. :shock:
Some care must be taken to isolate the jumper wire, if there's no soldermask on the board.
I will update soon.

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"Any intelligent fool can make things bigger, more complex, and more violent. It takes a touch of genius - and a lot of courage - to move in the opposite direction." Albert Einstein


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