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PostPosted: Sun Sep 09, 2012 5:42 am 
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Muriel
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Folks,

I came across an interesting article covering Clocks, especially in the context of a using FPGA's and/or CPLD's...

http://hifiduino.wordpress.com/category/diy-hifi/

I seem to be unable to work out how to link a single post in this stoopeed Wordpress site, if you happen to read this in halve a year or so search for: "Modding Clocks in USB-I2S Board?"...

The post is quite well reasoned, the only thing I would add is that it is of course possible to cancel the Jitter added by the FPGA/CPLD using a classic re-clocker driven directly by the oscillator...

Interesting analysis of the special "audio grade" Crystek Clock...

Ciao T

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PostPosted: Sun Sep 09, 2012 9:56 am 
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The URL to the post:
http://hifiduino.wordpress.com/2012/09/ ... i2s-board/

It's hidden... you have to click on the title of the post to get to its page.


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PostPosted: Sun Sep 09, 2012 10:03 am 
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Benjamin
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Kuei Yang Wang wrote:
Interesting analysis of the special "audio grade" Crystek Clock...


What is so interesting about it? Too much of a wimp to take the lid off. Pathetic! I know guys who have, so I have a good idea what is inside. (Wanna bet Elso won't be impressed...............)


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PostPosted: Sun Sep 09, 2012 12:12 pm 
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Blogger, yeah take off the lid, don't be shy. You can learn something perhaps

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PostPosted: Sun Sep 09, 2012 5:34 pm 
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Muriel
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Jocko,

Jocko Homo wrote:
What is so interesting about it?


How little is really in that 30 Bux clock?

I remember a recent debate here on how good a clock we could make...

I think we could make a better one than that... ;-)

The other point I like is that finally someone has grocked that low clockjitter is meaningless, unless the rest of the system is also low jitter and even the best engineering imposes limits there...

Ciao T

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PostPosted: Sun Sep 09, 2012 7:22 pm 
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Most engineers love all these fancy programmable devices. You really can perform wonderful computational feats at stupid high speed.

But, if you clock your converter with any output of one of these, you're either crazy, inexperienced, or incompetent. Even the converter manufacturers discourage this.


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PostPosted: Sun Sep 09, 2012 9:14 pm 
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Kuei Yang Wang wrote:
The other point I like is that finally someone has grocked that low clockjitter is meaningless, unless the rest of the system is also low jitter and even the best engineering imposes limits there...


Rubbish. It does no such thing. All it does is reinforce whatever comes out of those FPGAs is horrible. Trying to fix it, by putting a good clock into it, is stupid.

You fix it by reclocking after the signal comes out of it. Now, if you think a DAC behaves the same way, then maybe you are using the wrong DAC. Which is probably a lot of the modern ones. But they suck for a myriad of reasons.

As much as I think those $28 GPTs are way overpriced, you can hear the difference between them and the bog standard ones, made by any number of sources. (Including Craptek.) And that still is not good enough. Of course, you can believe any thing you want. I know differently.

As far as jitter is measured, and which method is best................that is a different subject, and probably will not be resolved. Digital guys like to talk in the time domain, but their ways of correlating them to the frequency domain leave much to be desired. And the way most of us frequency domain folks measure it is equally useless, as no one goes low enough in frequency. (Of course they don't, because the numbers would be horrible! And no one would buy their crap. Not to mention how much work is required to do it the right way.)


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PostPosted: Tue Sep 11, 2012 5:09 pm 
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Muriel
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Jocko,

Jocko Homo wrote:
Kuei Yang Wang wrote:
The other point I like is that finally someone has grocked that low clockjitter is meaningless, unless the rest of the system is also low jitter and even the best engineering imposes limits there...


Rubbish. It does no such thing. All it does is reinforce whatever comes out of those FPGAs is horrible.


I disagree. FPGA's add more jitter, but the best you can do, a single picogate, optimally implemented PSU wise, will add jitter to your clock.

Normal SMD IC's (I do not even want to talk about the old DIP Cases) have 100's of millivolt groundbounce in the leadframe and bondwire... That is inside the IC. There is a jitter performace limit right here...

Sure, if you have good stuff and you use it well you can get pretty low jitter.

As to how to measure, the analogue output signal of course.

I could not give a hoot if your clock is 0.001pS peak-peak jitter at 10Hz offset (I know it's a Phantsy number, it is used for emphasis) if the DAC's analogue audio output shows -70dB Skirts at 10Hz offset!

That is my point about system engineering.

If your system tracks "X" amount of jitter in through all sorts of ways, then having a clock with "Y" Phasenoise/Jitter where Y is much smaller than X is meaningless.

It's like having a super cleanroom, super aircon, filtering and exhaust gear, with all your employees in white suits and all that jazz, while there is a huge hole in the wall and a duststorm outside...

The best "X" amount you can do is limited by the IC's you use (unless you grid away the case and fit 0204 SMD Cap's to the lead-frame) and it usually is not a single digit number either...

Ciao T

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PostPosted: Tue Sep 11, 2012 5:41 pm 
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Kuei Yang Wang wrote:
It's like having a super cleanroom, super aircon, filtering and exhaust gear, with all your employees in white suits and all that jazz, while there is a huge hole in the wall and a duststorm outside...


Does "while those people with the white suits hold a water-balloon contest" count? Been there, done that :wave:
Not that the "cleanroom" was that clean anyway..


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PostPosted: Tue Sep 11, 2012 6:04 pm 
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Muriel
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Hi,

guido wrote:
Does "while those people with the white suits hold a water-balloon contest" count? Been there, done that :wave:
Not that the "cleanroom" was that clean anyway..


Well, to me the main thing is: "Did you have FUN!?"

If so, it counts...

Ciao T

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PostPosted: Tue Sep 11, 2012 6:10 pm 
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Yup..

"Miss Bond" was involved (a blond girl, bonding chips in the room with an acient bonding machine). Lots of girls at that place, soldering iron in one hand, tweazers in the other and soldering through a microscope. But not in the clean room.


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PostPosted: Tue Sep 11, 2012 7:57 pm 
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Kuei Yang Wang wrote:
I disagree. FPGA's add more jitter,


No kidding. We already know that.

Quote:
but the best you can do, a single picogate, optimally implemented PSU wise, will add jitter to your clock.


Prove it. How much? What is the jitter spectrum? (I know the answer, but I am not the one making the claims.)

Quote:
As to how to measure, the analogue output signal of course.


Unless you build clocks. What you do with them is your problem. I just know how good of a clock you need.

Quote:
I could not give a hoot if your clock is 0.001pS peak-peak jitter at 10Hz offset (I know it's a Phantsy number, it is used for emphasis) if the DAC's analogue audio output shows -70dB Skirts at 10Hz offset!


Then you have problems, and it is not the fault of the clock.

Quote:
That is my point about system engineering.

If your system tracks "X" amount of jitter in through all sorts of ways, then having a clock with "Y" Phasenoise/Jitter where Y is much smaller than X is meaningless.


Like I said...........you have problems. Clean it up!

Quote:
It's like having a super cleanroom, super aircon, filtering and exhaust gear, with all your employees in white suits and all that jazz, while there is a huge hole in the wall and a duststorm outside...

The best "X" amount you can do is limited by the IC's you use (unless you grid away the case and fit 0204 SMD Cap's to the lead-frame) and it usually is not a single digit number either...


You are starting to sound like those guys we both can't stand that demand DBTs and say everything sounds alike, and if you think it doesn't then you are only saying that because you are blinded by the fancy case.

See, the problem is.......................you are wrong.

Some of my associates have demonstrated, many times, that you can hear the effects (or really the lack thereof) of using a really good clock. Sent over stinking SPDIF. Now, we all know there is no way the internal guts of the RX doohickey are anywhere close to -90 dBc @ 1 Hz. Yet, you stick a clock that quiet into the SPDIF TX doohickey you can and will hear the difference. And it isn't subtle.

Unless you don't want to, because you don't believe that it will. You may not believe me, and I don't care. I know what I know, and anyone who tells me I am full of it...................well, there is another forum for guys like that. You all know where it is.

"Screw you guys, I'm going home."


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PostPosted: Tue Sep 11, 2012 8:00 pm 
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Benjamin
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Online jitter calculator:

http://www.silabs.com/support/Pages/phase-noise-jitter-calculator.aspx

It has the added benefit of telling you which of their POC doohickeys will work in your application! (Or so they claim. Take with a grain of salt.) Guess the old adage of there being no such thing as a free lunch applies here.


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PostPosted: Tue Sep 11, 2012 9:43 pm 
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Muriel
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Hi,

guido wrote:
"Miss Bond" was involved (a blond girl, bonding chips in the room with an acient bonding machine). Lots of girls at that place, soldering iron in one hand, tweazers in the other and soldering through a microscope. But not in the clean room.


Who want's be with a bunch of soldering iron wielding hotties in a "clean room" anway. Bring on the dirt! :shock:

Actually some of these soldering girls are hotter than their irons and I no longer have to bet they shag like minx... :P

Ciao T

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PostPosted: Tue Sep 11, 2012 9:44 pm 
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Muriel
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Jocko,

Jocko Homo wrote:
Then you have problems, and it is not the fault of the clock.

...

Like I said...........you have problems. Clean it up!


Alas, I DONT have these problems... I shall work harder to have them.

Here is what I have...

Attachment:
jitter.jpg


Ciao T


You do not have the required permissions to view the files attached to this post.

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