Kuei Yang Wang wrote:
I'll first have to fix the major design faults (including the fact that the DAC clips with full scale signals) before I can get back to measuring the impact of my trickery on the DAC's jitter.
Okay, fixing was easier than I thought. They simply left the mandatory resistor to set the output voltage off.
There is a space on the PCB for it, but it's empty.
Fit the required resistor and voila, output voltage is 2V and the distortion is way down.
Using the AP2 as source the jitter is pretty bad. In my normal jitter measurement setup the Window is -95dBFs to -140dBFs, well the jitter was "off scale".
Using my upcoming product Jitter is much better, but it seems the CS8416 has enough noise on the PLL clock to degrade the SNR from 112dB to 106dB, even if feeding the DAC a near zero jitter SPDIF signal.
So I was thinking...
Hey, ain't ESS making a big deal of their DAC's Jitter rejection, in Async Mode? Are they just making it up?
So I check, well there is a 24.576MHz clock on board, but it does not seem to have any real job. It is attached to the CS8416, which doesn't really need it to work, and not to the DAC which could probably use the clock and it's funky ASRC to clean up the jitter.
A quick look and unsolder a tiny SMD Resistor in the DAC's MCK line and feed it via 1/2" of wire the 24.576MHz clock. Voila, now the ES9023 meets it's specification and is indeed quite impervious to jitter and it nearly meets the datasheet spec.
Are we surprised that the resultant DAC sound a lot better? It still ain't a match for my async USB ES9023 DAC in measured and subjective performance, but I think with these two small changes it is worth at least the 90 Dollar plus duty one pays...
These modern "designers", maybe they should start the design by reading the datasheet?