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Hi sidiy,
Why? it work. Maxpou

Hi Max,
Your I/V stage is no longer a common base type. You have a passive I/V (simple resistor) followed by a gain stage (about x80 or so).
It is simple and it may work but technically speaking it is the worst of all solutions. The full scale signal is only 44mVpeak so a lot of low level resolution will be burried in noise and higher values for the resistors will not help much since this leads to worse linearity (higher THD). From what you seem to imply I gather that with 22ohms it is already bad.

I don't know what is 'hidden' inside the PCM1798 converter but presumably its output impedance is not higher than a few hundred ohms. Ideally it should be very high - like several hundreds of kohm, in order to allow us to hook a resistor directly at the output and get the right amplitude, all in one shot.

You are concerned about the 22 ohm Zin but not about the DC value developed across the resistor from the offset current that isn't being dealt with here, which is doing more harm to the dac linearity?

Also Ok I am not really convinced that 44mV peak from a a passive I/V is losing a lot of resolution amplified with a bjt gain stage. Too lazy to do the math but intuition tells me that smaller audio signals were amplified with tube stages in the 60's laying down master tracks that a lot of the "hirez" 24/96k remastered releases are buying today.

Hi glen,
I guess you missed my post on the previous page

Related to that I have not mentioned the excess noise issues in addition to thermal noise (avoidable at these voltage levels only if bulk foils are used).
Anyway
So Max it seems you have no choice, you really need to get back at the drawing board !

Hi Guys,
I'm back again. I returned on my first idea with the jocko circuit but I have a problem with the ajustment of it. I tried to ajust R7 for 0V at input and R8 for 0V at output without success but if I disconnect my DAC I don't have the problem with the ajustment. Why? Thank you! Maxpou

p.s.: I use the PCM1798 for my test.

you want to adjust to -2.5V on the input.

Hi,

no, with the PCMs You must not adjust to -2.5V at the input but to 0V, or You may risk destruction of the DAC.
The input beeing the emitter of the Jocko-circuits input transistor, sitting at 0V.
The output beeing the collector of the same transistor, sitting at a positive offset voltage of roughly 1/2 of the supply voltage.
The signal voltage needs to be ac-coupled with a cap to the following stage.
The level of collector voltage and collector current influences THD considerably.
With 0dBfs signal the miniumum collector voltage should not become too low..a couple of Volts should always be left.

jauu
Calvin

It looks to me like you have marginal bias current through Q3. According to the PCM1798 datasheet, it's outputs have a quiescent bias current of 3.5mA. Your schematic shows Q3 biased at only 4mA. Try doubling that bias current to 8mA by reducing Q3's emitter resistor R2 by half. In addition, you will need to increase the current through Q6 by 4mA.

In general, I suggest that you increase the bias currents thoughout your circuit. For example, the 1.9mA bias through the folded-cascode seems lower than optimum. Remember to commensurately increase the bias through Q6 to account for the total bias of Q3 and the folded-cascode. Don't forget to observe the power limits of all the transistors as you increase bias currents, particularly for Q6.

Hi,

couldn´t open the attchment for the afore answer of mine. Thought of a original Jocko, not a folded cascoded Jocko.
Well anyway, seeing the schematics now, its obvious as knewton already suggested, that the level of currents is too small.
The PCM puts out 4mApp (+-2mA), centered around -3.5mA.
So You need at minimum 2mA of current flowing from input via Q2 to have the full signal stroke processed, not the 0.5mA as in Your design.
The BC546 work well with currents between 4mA and 10mA, so a suggested idle current for Q2 might be 7mA-8mA.
The current trough Q3 then needs to be the sum of Q2´s idle current and the DAC´s centre current, hence 10.5mA-11.5mA.
The same as for Q2 applies to the folded part around Q5. knewton explained the situation very well.
Just a Q. What do You expect from the folded cascode?
Without some means of temperature compensation, the output will not idle at 0V. So You probabely need to ac-couple the output signal to a following buffer stage anyway.
Why not make it simpler and replace the (quite noisy) ccs Q6 by a simple 1.5k I/V-resistor and a small 150pF cap (the 2nF C1 is alot more than required) to gnd and ac-couple with a (small valued, high quality) cap (say 470nF) to a simple Buffer stage (JFET-ccs-loaded JFET)?
Also Q3 could be replaced by a simple JFET-ccs which introduces less noise. As JFETs the 4391 is fine.
Potis should not take on much current and usually feature high tempcos. A fixed resistor that takes on most of the current with a paralleled higher-ohmic poti may improve matters.
If Q1 and Q2 are well matched similar idle currents in Q1 and Q2 should lead to 0V at Q2s emitter.
Since Q1s collector voltage remains at Vbe, R7 takes over most of the power loss of this circuit branch. You can reduce the required current and hence the power losses through R7 and Q1 considerably by adding a small (probabely less than 10Ohms) resistance from Q1s emitter to ground. Beware though that such a resistor adds some noise.


jauu
Calvin

Hi Knewton and Calvin,
thank you for reply and explanations, now my IV stage work very well. I have 0Vdc at input and output with 2 Vrms of signal. But I changed the RIV, CIV for 2.7K and 560pF. Calvin for your question on folded cascode. I want built a circuit without coupling cap. If needed I will add a dc servo.

I do not understand why you said it takes a current of 10.5mA to 11.5mA for Q6. Look my schematic with all currents and resistor value.

Thank you! Maxpou

Hi Max,

first, congrats that the circuit is working.
As for Yout understanding. I wrote:

The important part here beeing the idle current through Q2.
In Your circuit Q2s current will only be Iq3-Idac --> 6.9ma-3.5mA=2.4mA
This is just marginally enough for a signal current stroke of +-2mA.
As result the THD will be quite high and the input impedance of the circuit is a bit higher.

jauu
Calvin

HI Calvin


Thank's again for reply,
I have a current of 3.4mA in Q2 ( 6.9ma-3.5ma=3.4mA). Yesterday I wanted to measure the distortion with my HP334 and an original Pansonic test disc, but my results are not possible because I have 0.00035% at 1kHz at 0dB and 0.00125% for 10Khz. I think my 334 is defect or I have not the right way. Thank you! Maxpou

Maxpou, Calvin is right, consider increasing the currents.
It would be best if you at least are going to double them.
To limit dissipation of the transistors, you may reduce the supply voltage, you do not need almost ±14V I think.

To achieve this, you can put a cap multiplier in both rails, set up to eat some volts. As the load is basically a ccs and some resistors to ground, you do not need a low impedance psu. Low noise is more important.

Hi zinsula,
I followed the advice of Calvin, I increased the current in Q6 at 10.5mA and Q4 for 0V at the output. I use this PSU for my IV stage if your comments guys are welcome. Thank you! Maxpou

Assuming that D5 and D6 are zener diodes (what voltage btw?), you should inverse polarity of D7 and D8.

Check out for oscillations, I had something similar (two emitter followers), and depending on the elcap ath the output they did oscillate. Not sure if C19/C20 are a good thing, but you really have to check with an oscilloscope.