Look up the specs of the IC and you might get an idea what it can do. I dont' see why you should presume it's not working as part of a PLL either.
My EMU Audiodock uses a set of Xilinx chips as well and it IS part of a PLL.
What they did to the clock lines after that at least from the purists perspective is an fn disgrace, but it's also been made to sound surprisingly decent.
My guess is as I think others have already stated, these guys are just copying what they've seen a dozen others do.
Which IC are you talking about the Cypress is USB controller/streamer pretty much like a TAS1020B with internal 8051 mcu and all. The FPGA ic specs - I don't have a clue. I'm not particularly interested in their analog out but it would be a bonus if it was any good. PCM1793 DAC, not stellar but probably can be good. IV stage would have to be changed, as usual.
You're right, I should have said that it doesn't use analog PLL. I don't know about digital PLL in FPGA. How good can this be?
Copied who? Who has asynch USB running on FPGA at 24/192KHz? It all really boils down to their clock & how low the added jitter is in the system.
Edit: I saw reference to sarin clock management in the translated text for this DAC but didn't know what, if anything, this referring to. Based on your probing, TD, I researched and found reference to this http://www.actel.com/documents/DigitalPLL_AN.pdf
which mentions "Jitter-Bounded Digital PLL" using Successive Approximation Register (SAR) - could this be the FPGA PLL technique used?