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Hi

I need some advice from the digital experts on the best way to improve the clock/reclocking in this CDP. The schematics are attached below.

The existing arrangement uses a hex inverter (Z206) for the clock and distribution. A dual flip flop (Z207) is used to reclock BCK. The reclocked BCK then passes through the inverter before going to the dac. I assume this is to reduce the effects of any delay as WS and DATA are not relcocked.

I am planning to install a Tent XO2 clock module which has three outputs. One output could be used to drive the existing dual flip flop. Another output could be used to drive an additional dual flip flop to relcock WS and DATA. The third output could be used to connect to the SAA7220 filter.

This would mean that the hex inverter would no longer be required and could be replaced by the new dual flip flop.

Is my understanding of the workings correct and what do you think of this proposal?

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Totally Arcamental

Yes, that is right. Ditch the hex inverter.

However........I would use of one those outputs to drive the decoder chip. You can not use the internal buffer in the filter to drive anything.

And, of course.........the most important part of all: you have to drive the DAC chip from the new clock. Unless you do, you are wasting your $$.

Jocko

Thanks Jocko



OK - I'll remove the crystal and its associated components and the hex inverter. Then I'll need to connect anything that was passing through the inverter directly to its source, ie. BCK from flip-flop directly to pins 2 & 4 of TDA.



So - cut the track between the filter and decoder - and connect one output of the colck in there.



How is this done? TDA1541A only has a BCK input on pin 2 (which is connected to pin 4). BCK comes from the filter and is relcocked with a flip-flop. This flip-flop would be driven by the new clock.

Regards
Fin

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Totally Arcamental

If you stick that fancy clock into pin whatever of the filter chip (which is the stock way it is usually done), you won't have gained anything. There is so much stuff going on inside of the filter chip, that it makes little difference on what comes out of the pin that they use to drive everything.

Maybe your unit is a bit better designed, but most that I have seen feed the DAC and decoder from the filter. You can't do that.......anything that gets a clock signal must get it from the clock, not the oscillator chip.

Does that help any?

Jocko

Are you saying that I should get rid of the connection for the bitclock (BCK) between the filter and DAC - which is reclocked - and replace it with a direct connection from the new clock to the DAC?

Fin

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Totally Arcamental

This is how the master clock is described in the service manual:

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Totally Arcamental

That's a horrible schematic......making it hard for us old farts to read, eh?

I can't see why you would reclock a signal with itself. Since it is a dual flip-flop, it can possibly add jitter......even if you only use 1/2 of it. Looks like they are using the compliment output to drive something else. Probably some other reclocker downstream.

Anyway.......yeah, drive it direct. I would.

Jocko

Oh......one of those kind of flip-flops. OK.....I can see getting rid of the crappy circuit that Philips uses.......

Never saw a reason to divide the clock by 2. Wonder what other odd things that they have done to screw with us.

Jocko

Sorry - it's the best I can do within the allowable file size. Happy to email you a better copy.



One half of the 74HC74 reclocks the bitclock and the other half is used for the SPDIF output.



At 11.2896mHz? Max bitclock frequency is 6.4mHz in the datasheet.

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Totally Arcamental

Thanks for sending me that. (Hint of sarcasm, after it took 10 minutes to d/l............)

Now that I can almost read it......

Forgot about that problem when you use the stock parts: the DAC works at 128 * Fs. I haven't done that in over 12 years, so you had to jog my memory.

Yep, you have to either divide the 256 * Fs clock by 2, or reclock the clock coming out of the filter. Since it is already set up to do the former, might be best to leave it that way. But..........I would disable the other half of the flip-flop. It would be better to use a separate one if you need the digital output. The more stuff that chip has to do, the more jitter it will introduce. Both signals would benefit from that.

I would still drive the decoder chip form the improved clock module, rather than the output (pin 9) of the filter chip.

Jocko

Sorry about that! Guess we are both old timers still on dial up.


No worries! I know you are not a fan of this chip.


OK - this is what I'm really interested in. If I leave it that way, ie. reclock the clock coming from the filter, do I still need to pass this clock through the inverter (Z206-B pins 3&4)? Is this only done because WS and Data are not reclocked? If I find a way to reclock WS and Data - what then?


Don't plan to use the digital output - so what's the best way to disable that half of the flip-flop?



A direct connection from the new clock to the decoder? Can I just ignore the inverter?

I'm hoping to get to a stage where I can remove the inverter chip completely - but still have everything clocked correctly.

Thanks
Fin

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Totally Arcamental

Ditch the inverter. It has no effect on whether you reclock or not.

As for the flip-flop........tie the inputs high.....or low.......which ever is easier.

Jocko

Hi Jocko

Saw your avatar in a video clip yesterday!

So - I can safely remove the hex inverter, connect the output of the flip-flop directly to the dac, disable the other side of the flip-flop, connect one output of the XO2 to the flip-flop, another output to the decoder and the third output to the.........filter? Does the filter need it or does it use the bitclock from the decoder?

If I add more flip-flops to reclock WS and DATA - can they share the output going to the original flip-flop?

Fin

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Totally Arcamental

The ARCAM circuit would have been good ? if only it had been done properly, and ARCAM had not resorted to ?Penny Pinching? in critical areas.

While the circuit diagram is OK, using the shared packaged HCU04 to function as the XO circuit and Digital output buffer, and likewise the dual co-packaged 74HC74 to re-clock the BCLK & Digital output is just a waste of time.

As the co-packaged gates share the same VDD & Ground pins, isolation is very poor. In both cases the Clock will be directly modulated by the SPDIF Digital output. The resultant Phase noise (jitter) is directly data related ? Jitter of the worst kind.

CMOS is capable of better performance then most people believe ? however don?t share Gates / Logic in co packaged parts. I use the 5V single Gate Fairchild ?Tiny Logic? or ?Pico logic? with ?state of the art? results.

John

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Hi-Fi??? "I may not be a psychiatrist but I know insanity when I see it - what ever happened to the normal old pervert who was content to sniff bicycle seats and collect women's shoes anyway?"

Thanks John

So - if I install the Tent XO2 and do as Jocko suggests by ditching the HCU04 and disable the side of the 74HC74 dealing with the SPDIF out - that should inprove things?

At that point - WS and DATA won't be reclocked. I understand that it is optimal to use a separate IC to reclock each signal line - but if that is not possible or convenient - what is the next best option? Would it be better to leave WS and DATA not reclocked - or the reclocked them using shared logic?

Fin

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Totally Arcamental