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PostPosted: Thu Aug 04, 2011 12:52 am 
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Yes, Pedja is absolutely right.
I can get with our IV+filter (as they are) the THD at 0.006% (H2 at more than 88dB under the fundamental). But for this I have to use only 0.225mA from the DAC. This post and the next one contain those type of trick measurements. I'm also using a circuit that simulates as close as possible the output Z of a real DAC.

OTOH one can cheat a bit (actually a lot) by swinging more volts into a higher value Zout-resistor to get the same current levels and much lower distorsions.


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PostPosted: Thu Aug 04, 2011 5:55 am 
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Hello Glen, glad you like it.
I'm answering you later because I had some homework to do (never saved those sims). But first the THD plots are here. There must be a slight confusion when you are referring to first IM +/-60Hz around the 7kHz; these are produced by a 60Hz tone that sits 12dB above the level of the 7kHz.

I did my sims while the IV was 'evolving' and I explained my preference for the AD743 and the initial mistake I did when choosing the ratio between R8/R7 and R7/R6.
The logical thing to do now (as first major upgrade), since we're not using the Gain scaling feature anymore, is:
- add a fixed current source (~9mA) to the collector of Q8
- increase R8 about ten times
This should give the servo a limited adjustment range (+/-1 mA) just enough to cope with the thermal variations (which are quite low anyway), but would reduce the (eventual) audible signature to "hard to fault" level :grin:

But even as it is we're 80dB away in midband (I hope that the Gootee type sims refers to that, I need to do a search)


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PostPosted: Thu Aug 04, 2011 5:58 am 
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Servo detail with the test points.


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PostPosted: Sat Aug 06, 2011 3:18 pm 
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Very good thread at diya, tackles a with a lot of servo issues (thx glen).
Chapeau to Tom Gootee. For those who can't 'see to the other side' here is his webpage.

Our servo had to be slooow...1M and 2u2, mute at power on lasts 6secs.


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PostPosted: Sun Aug 07, 2011 12:06 am 
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Yes Gootee's servo analysis was a real eye opener for me, glad you found the info useful.


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PostPosted: Mon Aug 08, 2011 3:13 am 
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A thread featuring the PMD100 filter would not be complete without clarifying the reclocking issues and showing the output signals, which are far from the classical format. I hope it will help other diy-ers unfamiliar with this circuit. However the screenshot and comments apply only to our application: PMD is in 384Fs mode and the output is 20bit.

I had a lot of trouble in the beginning understanding this part, quote from the datasheet: “Although the PMD-100 accepts either 256 or 384 Fs, its output timing is based upon a 256 Fs system clock with a changing duty cycle.” This catch phrase is supposedly enough to describe what is happening in the next image, well…for a few chosen ones, certainly I needed help.

In yellow is WCKO (LE for AD1862), needs reclocking since the negative edge updates the DAC output. Not really 50% duty cycle as we’ve been accustomed.
In cyan is one of the data lines, I played a full scale signal so all bits are active at some point.
In magenta is the BCKO, its rising edge must occur somewhere in the middle of a (stable) data bit to ‘load’ it correctly into DAC registry. The fun part starts here, its duty cycle is not 50% either, looks more like 2/3, which leads us to believe that the 16.9MCLK is doubled and divided by 3 internally (duh!... obvious)… Thus the warning concerning extra jitter in 384Fs mode because WCKO must be originating from the same ‘reference’.

Personally I don’t see any benefit in reclocking Data and BCKO, but related to that another concern arises. The internal switches/current sources in a AD1862 take 0.35us to settle. In order to have a really silent conversion we don’t want to see any activity/ground bounces during that time on the digital side. Or exactly the opposite happens, the first data bit may arrive as soon as 0.16us after the negative going WCKO.

It may be a good idea to delay these two lines for another 0.2us using for instance a couple of slower (non)inverting gates in series (+ a carefully chosen resistor in the middle). Of course component values and parasitics for these two signal lines must not be wildly different to maintain their timing relationship. I don’t know what the propagation delay for the CMOS 4000 family is these days, some are modernized and quite ‘speedy’.
I somehow shelved this idea, although there was a Bart Simpson moment (bad probe ground as discovered later) back here :D
Anyway, I hope it helps :good:


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PostPosted: Mon Aug 08, 2011 7:06 am 
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What is your opinion of the PMD software mode dither, are they substantially better than the hardware dither mode of the PMD100 ?


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PostPosted: Tue Aug 09, 2011 1:20 am 
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Hopefully the following photos are a good substitute for my lack of knowledge on this subject. There must be some maths behind this that show why a 1bit type DAC needs a type of dither with a certain distribution function vs a multi-bit that needs another type.

I took the datasheet at face value so I did not even tried DM0 (default) or DM7. In my opinion the dither feature is the only one correctly implemented, for us Dither Mode 1 is giving the best results. To correctly evaluate the effects of DM0 versus the others I should change the PIC code and run the same measurements again...st my schedule :blush: If you need the code, it's not classified so just shoot me an e-mail, at least that I can do in a timely manner. I can only speculate that the out of band noise curve might bent differently and the frequency at which the lsb's are randomized might not "fully" linearize a multibit DAC.

However I had a Rotel player for a while and I saved the following image (for a -90.3dB signal without dither). They use the PMD in hardware mode with Dither Mode0 engaged all the time. Dither is also scaled for 20bit output since the DACs used are PCM63. I guess nobody can extract a FFT out of this... :banghead: It looks like the 16b stairwell shape is not visible anymore (which is what we want) but it has a certain roughness for a sine approximation. (disclaimer: nothing to do with listening, I hope I'm not coining a new term).


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PostPosted: Tue Aug 09, 2011 2:53 am 
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Not a contest, here is our CDP with DM3 and the same signal.
(note: out level for the Rotel is 2.2Vrms vs our player 1.96Vrms)

Eager to evaluate the feature I did quite a few headphone listening tests (before and after having the EMU card for measurements) and I can say that there may be a correlation:
- No dither is the typical dark, spacious kind of sound, I kind of like it -> against the standing theory that clearly says that dither should be applied whenever truncation occurs...and since internally the PMD works at 24b or more...
- DM1 preserves the character above but seems more fluid -> ? less distorsions and idle tones ?
- DM2, DM3, (DM4) are correct but have progressively less dynamics and details - not very fond of either, 'not interesting' category
- (DM4), DM5, DM6 listenable but they clearly have tape hiss (white-noise) -> too much of a good thing, denotes that a second order low pass can't cope with that level of noise

The design choices for the analog stage (own noise, distorsions, filter order) have clearly an impact on which DM is preferred... in the end... the more the merrier, how they say. I hope it answers at least partially your question.

It takes some training to spot these differences when listening with loudspeakers, except for DM5, DM6 close to the tweeters.

DM4 is borderline hence the ().


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PostPosted: Fri Sep 23, 2011 7:19 am 
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This has to be the most informative thread I've seen in a long time. Congrats to sidiy for completing such a bold project!

I have a question about the digital lines though. You hold the BCK and data lines at zero when the dac is not receiving data. Would there be any measurable noise from not doing this? I mean if the dac receives data outside of the 20-bit window of data that is latched.

I'm in the preliminary stage of my own AD1862 project. 74HC-logic will be used to correctly align the I2s data. But since I'll be running higher sampling frequencies I hope to cut the IC count short and sweet.


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PostPosted: Sun Sep 25, 2011 12:47 pm 
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Hi,
If I understand correctly you want to use something different than the PMD100, with 16x oversampling or some higher rates of 48kHz.
It is important to obtain the WCKO as a re-clocked version of the crystal osc, divided according to your app. Activity on other digital lines right before and after the negative going WCKO will produce ground bounces that will "jitter" this signal and as a consequence the analog out too.

Ideally you should use an independent clean supply for your osc. and reclock circuitry....(devil is in the details :grin: )


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PostPosted: Wed Sep 28, 2011 6:40 am 
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I'm not running any digital filter as such. Only 192 kHz upsampled material from USB -> I2s, then directly to the dac. 74HC164 shift registers for correct data alignment and a quad input NOR gate for appropriate silencing of the data lines.

But at 192 kHz I quickly reach the limit for tolerable propagation delay. I need two 74HC164 for correct data alignment, then two NOR gates for right/left silencing. That's suddenly a 38 ns delay on the data lines. Perhaps reclocking all lines through a 74HC574 afterwards could work?


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PostPosted: Mon Oct 03, 2011 6:54 pm 
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Hi, sorry for the delay (definitely higher than 38ns... :grin: )
I don't have all the details about the upsampling process used but I hope you have a dithering scheme in place when truncating down from 24b to 20b. Or that the ASRC chip has a proper selectable 20b output format.

About the rest... I need a schematic to figure out the delays and what you're trying to do. It looks like you've chosen an interesting (less standard) solution...no oversampling but high enough sample rate...


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PostPosted: Thu Oct 06, 2011 8:11 am 
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I was thinking something along the lines of this:
Attachment:
Bit shift register.jpg


The first two 74HC164's shifts the signal 11 bits to the right. The extra four 164-chips are only for delaying the other channel another 32 bits, for simultaneous conversion, which I find useless. In addition I would be using a quad NAND gate for silencing the data line when the opposite word is transmitted.

I'm using the exaDevices USB->I2s receiver. It's a 32 bit/384 kHz capable asynchronus Xilinx-based board. http://www.exadevices.com It outputs standard I2s format with a clock frequency of 11.28 MHz for 174.4 kHz, or 12.29 MHz for 192 Khz. For playback I use J.River Media Center, which upsamples the signal to 174.6 kHz on the fly. The software operates at 64-bit floating point with dithering and the output to the USB receiver is 32-bit. Right now I'm feeding the I2s signal DIRECTLY from the receiver to the dac. (Ok, I'm using one 74HC02 NAND gate.) The correct alignment of the data is achieved by dividing by 2^11 in the software, ie. reducing volume by exactly 20log(2^11) dB = 66,2265990... dB.

This is a rediculously simple solution. It's also quite an unusual approach I believe. I'm surprised that it actually works.


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PostPosted: Wed Nov 02, 2011 2:17 am 
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Excellent news!
I can't post in the 'Forum open again' thread for some reason.
But nonetheless the old crew did a great job and I join my thanks to them! :clapping: Their time permitting, I hope they will continue to contribute as regular posters!

And good news for the BEG project, I will continue it here (and hopefully many others to come...) :thumbsup:


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